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Microchip Technology /ATSAML11E16A /MPU /MPU_RBAR

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Interpret as MPU_RBAR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (XN)XN 0 (RWPRIV)AP0 (NO)SH0BASE

AP=RWPRIV, SH=NO

Description

MPU Region Base Address Register

Fields

XN

Execute Never
AP

Access permissions

0 (RWPRIV): Read/write by privileged code only

1 (RWANY): Read/write by any privilege level

2 (RPRIV): Read-only by privileged code only

3 (RANY): Read-only by any privilege level
SH

Shareability

0 (NO): Non-shareable

2 (OUTER): Outer shareable

3 (INNER): Inner shareable
BASE

Base address

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data